This invention relates in general to digital clock circuits and, more particularly, to a digital clock circuit for aligning the edges of a low speed clock signal to a high speed clock signal.
Many digital systems use two or more clock signals operating at different frequencies for transferring data through the system. A common procedure for generating a high frequency clock and a low frequency clock is to feed an external clock source into a phase lock loop (PLL) and develop the high speed clock signal at the output of the voltage controlled oscillator (VCO) of the PLL. The low speed clock may be taken at the output of a divide-by-N circuit in the feedback path between the output of the VCO and the phase detector of the PLL, as is well understood. The high speed and low speed clock signals are routed throughout the system to perform the intended functions.
The logic circuit using the high speed and low speed clock signals may be a considerable distance from the PLL generation source. Therefore, the transitions of the high speed clock signal and the low speed clock signal can become mis-aligned at various points in the system primarily due to differences in propagation delay and capacitive loading in the different paths. In many applications, it is critical to have accurate alignment of the high speed clock signal and the low speed clock signal at the point of utilization. Otherwise, data may be clocked at the wrong points resulting in invalid data transfers. Thus, circuit designers have typically invested considerable time and effort into detailed analysis of the propagation paths to ensure proper alignment of the high speed and low speed clock signals at key points in the system. Unfortunately, the difficulty in aligning the clock edges of the different frequency clock signals often forces the designers to use more setup and hold time for the data transfers which limits the operating speed and bandwidth of the system.
Hence, what is needed is an improved clock generation circuit for providing proper alignment between the clock edges of the high speed and low speed clock signals at the point of usage.